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Abstract This work reports on the hardware implementation of analog dot-product operation on arrays of 2D hexagonal boron nitride (h-BN) memristors. This extends beyond previous work that studied isolated device characteristics towards the application of analog neural network accelerators based on 2D memristor arrays. The wafer-level fabrication of the memristor arrays is enabled by large-area transfer of CVD-grown few-layer (8 layers) h-BN films. Individual devices achieve an on/off ratio of >10, low voltage operation (~0.5 Vset/Vreset), good endurance (>6,000 programming steps), and good retention (>104 s). The dot-product operation shows excellent linearity and repeatability, with low read energy consumption (~200 aJ to 20 fJ per operation), with minimal error and deviation over various measurement cycles. Moreover, we present the implementation of a stochastic logistic regression algorithm in 2D h-BN memristor hardware for the classification of noisy images. The promising resistive switching characteristics, performance of dot-product computation, and successful demonstration of logistic regression in h-BN memristors signify an important step towards the integration of 2D materials for next-generation neuromorphic computing systems. 

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. 

Abstract Previous work that studied hexagonal boron nitride (h‐BN) memristor DC resistive‐switching characteristics is extended to include an experimental understanding of their dynamic behavior upon programming or synaptic weight update. The focus is on the temporal resistive switching response to driving stimulus (programming voltage pulses) effecting conductance updates during training in neural network crossbar implementations. Test arrays are fabricated at the wafer level, enabled by the transfer of CVD‐grown few‐layer (8 layer) or multi‐layer (18 layer) h‐BN films. A comprehensive study of their temporal response under various conditions–voltage pulse amplitude, edge rate (pulse rise/fall times), and temperature–provides new insights into the resistive switching process toward optimized devices and improvements in their implementation of artificial neural networks. The h‐BN memristors can achieve multi‐state operation through ultrafast pulsed switching (< 25 ns) with high energy efficiency (≈10 pJ pulse⁻¹).